instruction stringlengths 27 385 | output stringlengths 355 1.9k |
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Design a non-inverting op-amp amplifier with a voltage gain of +1000 V/V. Use R1=1kOhm. Model the op-amp as an ideal VCVS. Provide topology selection reasoning, derive Rf from the gain equation, and write the complete ngspice netlist. | Phase 1 -- Circuit Identification
Specification: non-inverting amplifier, Gain = +1000 V/V, R1 = 1kOhm.
Topology selection: non-inverting op-amp configuration.
- Signal applied directly to the non-inverting (+) input.
- Output in phase with input (no inversion).
- Input impedance is essentially infinite (op-amp i... |
Produce a SPICE netlist for a inverting Schmitt trigger achieving Vhys=1.0V, ±3.3V, R1=30k, Rf=100k. | Phase 1 - Circuit Identification
An inverting Schmitt trigger uses positive feedback to the non-inverting (+) terminal to create hysteresis. Upper threshold VUT and lower threshold VLT differ by Vhys, preventing false triggering on noisy signals.
Phase 2 - Design Equations
-> substituting: Rf = 100 k
Vhys = 2*Vsat*R... |
Provide a complete SPICE netlist for a RC phase-shift oscillator with f0=500Hz, R=6.8k, C=18nF. | Phase 1 - Circuit Identification
An RC phase-shift oscillator uses a BJT common-emitter amplifier with three cascaded RC sections each contributing 60deg phase shift (180deg total). Combined with the amplifier's 180deg inversion, the loop phase is 360deg. Barkhausen criterion met when |Av| >= 29.
Phase 2 - Design Equa... |
Write a minimal ngspice .subckt definition for 'OPAMP' with ports 'in', 'ref', 'out'. Use a VCVS with gain=100k. | Phase 1 -- Element Identification
A subcircuit block in SPICE uses .subckt/.ends. General syntax:
.subckt <name> <port1> [<port2> ...]
<internal elements>
.ends <name>
Port names are local. Instantiate with X<instance>.
Phase 2 -- Parameter Mapping
-> substituting: name=OPAMP, ports=in ref out
Phase 3 -- Usage Note... |
Generate a SPICE netlist for a RC phase-shift oscillator achieving f0=500Hz, R=3.3k, C=39nF. | Phase 1 - Circuit Identification
An RC phase-shift oscillator uses a BJT common-emitter amplifier with three cascaded RC sections each contributing 60deg phase shift (180deg total). Combined with the amplifier's 180deg inversion, the loop phase is 360deg. Barkhausen criterion met when |Av| >= 29.
Phase 2 - Design Equa... |
Write an ngspice-compatible netlist for a Wien-bridge oscillator with f0=50kHz, R=13k, C=220pF. | Phase 1 - Circuit Identification
A Wien-bridge oscillator uses a non-inverting op-amp with a Wien-bridge frequency-selective network. At f0, the bridge gives +1/3 gain and 0deg phase shift. With Av = 3 (Rf = 2Rg), the Barkhausen criterion is met.
Phase 2 - Design Equations
f0 = 1/(2piRC) = 50kHz
-> substituting: R=1... |
Give me an ngspice netlist for a NMOS enhancement-mode switch with Vdd=24V, Rl=510, Rg=910. | Phase 1 - Circuit Identification
An NMOS switch turns ON when Vgs > Vth (~= 2 V). No DC gate current, so no base resistor current drain. Gate resistor prevents oscillation and limits dv/dt on the gate.
Phase 2 - Design Equations
-> substituting: Vdd = 24, Rg = 910 Ohm, Rl = 510 Ohm
ON condition: Vgs = 3.3 V or 5 V >... |
Give me an ngspice netlist for a RLC series resonant circuit with f0=2kHz, R=82, L=330uH, C=18uF. | Phase 1 - Circuit Identification
A series RLC circuit exhibits resonance when XL = XC. At resonance f0, impedance is minimum (= R) and current is maximum. Q factor determines bandwidth: BW = f0/Q.
Phase 2 - Design Equations
f0 = 1/(2pisqrt(LC)) = 2kHz
-> substituting: L=330uH, C=18uF
Choose L, then C = 1/(2pi*f0)_/L... |
Implement a BJT current mirror in SPICE achieving Iref=2.0mA, Vcc=12V, Rref=5.6k. | Phase 1 - Circuit Identification
A BJT current mirror uses two matched transistors sharing the same Vbe. Q1 is diode-connected, setting Vbe. Q2 copies the same Vbe, mirroring the reference current. Output tracks Iref independent of load voltage (matched devices assumed).
Phase 2 - Design Equations
-> substituting: V... |
Produce a SPICE netlist for a peak detector achieving hold capacitor C=33nF, discharge resistor R=220k. | Phase 1 - Circuit Identification
A peak detector captures and holds the maximum amplitude of the input. The diode charges the capacitor to Vpeak. Between peaks, the capacitor discharges slowly through R (tau = RC >> 1/f), maintaining the peak voltage at the output.
Phase 2 - Design Equations
-> substituting: R = 220... |
Create a NMOS source follower (common-drain) netlist with Id=20.0mA, Vdd=5V, Rs=120. | Phase 1 - Circuit Identification
A source follower applies signal to the gate and takes output at the source. Av ~= 1, no phase inversion. Very high Zin (gate); low Zout (~=1/gm). Used as buffer between high-Z source and low-Z load.
Phase 2 - Design Equations
-> substituting: Vdd = 5
Av ~= gm*Rs/(1+gm*Rs) ~= 1
Rs = ... |
Write an ngspice-compatible netlist for a bridge rectifier with Vp=30V AC, Rl=1.1k. | Phase 1 - Circuit Identification
A bridge rectifier uses four diodes arranged in a bridge. Both half-cycles are rectified, routing current through the load in the same direction. No centre-tap transformer needed. PIV per diode = Vp.
Phase 2 - Design Equations
-> substituting: Rl = 1.1 k
Vdc = 2Vp/pi ~= 19.1 V
PIV pe... |
Provide a complete SPICE netlist for a two-input inverting summing amplifier with gains −8.0/−1.0, Rf=24k, R1=3k, R2=24k. | Phase 1 - Circuit Identification
A summing amplifier uses the virtual-ground property of the inverting terminal to sum multiple input currents. Each input is scaled by its own resistor, then summed into Rf. Output: Vout = -(Rf/R1*V1 + Rf/R2*V2).
Phase 2 - Design Equations
Vout = -(Rf/R1 * V1 + Rf/R2 * V2)
-> substit... |
Design a dual diode clipper with clip levels ±2.0V, Rs=30k. | Phase 1 - Circuit Identification
A dual (bilateral) clipper limits both positive and negative peaks. D1 clamps at +2.0 V; D2 clamps at -2.0 V. Used for waveform shaping and protecting downstream circuits.
Phase 2 - Design Equations
Output: -2.0 <= Vout <= +2.0
Two diode-bias pairs, one per polarity.
Phase 3 - Componen... |
Provide a complete SPICE netlist for a zener voltage reference with Vz=12V, Vin=15V, Iz=0.5mA, Rs=6.2k. | Phase 1 - Circuit Identification
A zener diode reference operates the zener in reverse breakdown to produce stable output Vz. Series resistor Rs limits current. Zener voltage is largely independent of Iz over its operating range, giving good line regulation.
Phase 2 - Design Equations
Rs = (Vin - Vz)/Iz = (15 - 12)/0.... |
Design a first-order RC high-pass filter with fc=200kHz, R=100k, C=47nF. | Phase 1 -- Circuit Identification
A first-order RC high-pass filter passes high frequencies and attenuates low frequencies at +20 dB/decade below fc = 1/(2*pi*R*C). C is in series; R shunts to ground.
Phase 2 -- Design Equations
fc = 1/(2*pi*R*C) = 200kHz
-> substituting: R=100k, C=47nF, fc_actual=0.03kHz
RC = 1/(2*... |
Write an ngspice-compatible netlist for a difference amplifier with gain 20 V/V, R1=R3=3.3k, R2=R4=68k. | Phase 1 - Circuit Identification
A difference amplifier subtracts two input voltages and amplifies the result. With matched resistor ratios (R2/R1 = R4/R3), Vout = (R2/R1)(V2 - V1). CMRR depends on resistor matching accuracy.
Phase 2 - Design Equations
-> substituting: gain = 20
Vout = (R2/R1) * (V2 - V1) = 20 * (V2... |
Perform an AC frequency sweep on a RC Low-Pass filter with fc=0.5kHz, R=10k, C=470nF. Use 20 points per decade. | Phase 1 -- Circuit Identification
A first-order RC Low-Pass filter (R in series, C to ground) has a -3dB point at fc = 1/(2*pi*R*C). AC analysis sweeps the input frequency to reveal gain and phase vs. frequency.
Phase 2 -- Design Equations
fc = 1/(2*pi*R*C) = 0.5kHz
-> substituting: R=10k, C=470nF, fc_actual=0.03kHz... |
Construct an ngspice netlist for a NMOS common-source amplifier with Id=15.0mA, Vdd=15V, Rd=510, Rs=100. | Phase 1 - Circuit Identification
A common-source MOSFET amplifier applies input to the gate and takes output at the drain. The source is AC-bypassed. Rd sets voltage gain (Av = -gm*Rd). Gate draws no DC current, simplifying bias.
Phase 2 - Design Equations
-> substituting: Vdd = 15
Drain current: Id = 15.0 mA
Rd = V... |
Design a first-order RC high-pass filter with fc=2kHz, R=4.7k, C=2.2nF. | Phase 1 -- Circuit Identification
A first-order RC high-pass filter passes high frequencies and attenuates low frequencies at +20 dB/decade below fc = 1/(2*pi*R*C). C is in series; R shunts to ground.
Phase 2 -- Design Equations
fc = 1/(2*pi*R*C) = 2kHz
-> substituting: R=4.7k, C=2.2nF, fc_actual=15.39kHz
RC = 1/(2*... |
Give me an ngspice netlist for a RLC series resonant circuit with f0=500kHz, R=120, L=18mH, C=5.6pF. | Phase 1 - Circuit Identification
A series RLC circuit exhibits resonance when XL = XC. At resonance f0, impedance is minimum (= R) and current is maximum. Q factor determines bandwidth: BW = f0/Q.
Phase 2 - Design Equations
f0 = 1/(2pisqrt(LC)) = 500kHz
-> substituting: L=18mH, C=5.6pF
Choose L, then C = 1/(2pi*f0)_... |
Generate a SPICE netlist for a op-amp integrator achieving f0=20kHz, R=6.8k, C=1.2nF, τ=0.008ms. | Phase 1 - Circuit Identification
An op-amp integrator replaces the feedback resistor with a capacitor. Output: Vout = -(1/RC)_Vin dt. Gain rolls off at -20 dB/decade below the corner frequency.
Phase 2 - Design Equations
-> substituting: f0 = 20 kHz, R = 6.8 k, C = 1.2 nF
Transfer function: H(s) = -1/(sRC)
Corner: f... |
Generate a SPICE netlist for a BJT common-base amplifier achieving Ic=20.0mA, Vcc=12V, Rc=300, Re=62. | Phase 1 - Circuit Identification
A common-base configuration connects the base to AC ground via bypass capacitor. Input enters the emitter; output is taken at the collector. Current gain < 1 but voltage gain is high. Low Zin (~= re) and high Zout make it useful at RF.
Phase 2 - Design Equations
-> substituting: Vcc ... |
Perform an AC frequency sweep on a RC Low-Pass filter with fc=1kHz, R=22k, C=1000nF. Use 20 points per decade. | Phase 1 -- Circuit Identification
A first-order RC Low-Pass filter (R in series, C to ground) has a -3dB point at fc = 1/(2*pi*R*C). AC analysis sweeps the input frequency to reveal gain and phase vs. frequency.
Phase 2 -- Design Equations
fc = 1/(2*pi*R*C) = 1kHz
-> substituting: R=22k, C=1000nF, fc_actual=0.01kHz
... |
Provide a complete SPICE netlist for a NMOS source follower (common-drain) with Id=8.0mA, Vdd=24V, Rs=1.5k. | Phase 1 - Circuit Identification
A source follower applies signal to the gate and takes output at the source. Av ~= 1, no phase inversion. Very high Zin (gate); low Zout (~=1/gm). Used as buffer between high-Z source and low-Z load.
Phase 2 - Design Equations
Av ~= gm*Rs/(1+gm*Rs) ~= 1
Rs = (Vdd/2)/Id ~= 1.5 kOhm
->... |
Write an ngspice-compatible netlist for a positive diode clamper with Vbias=-1.5V, C=1.2uF, R=120k. | Phase 1 - Circuit Identification
A diode clamper shifts the entire waveform so that the peak (or trough) is clamped to a reference voltage Vbias. The capacitor stores the DC shift; the diode sets clamping direction; R provides a discharge path.
Phase 2 - Design Equations
Vout_min ~= Vbias (positive clamper, clamps neg... |
Design a first-order RL high-pass filter with fc=2kHz, R=1.3k, L=82mH. | Phase 1 - Circuit Identification
An RL high-pass filter places the resistor in series and the inductor to ground. At high frequencies the inductor is high impedance, blocking the shunt path and passing the signal. At low frequencies the inductor shorts the output. fc = R/(2piL).
Phase 2 - Design Equations
fc = R/(2pi*... |
Write the ngspice SIN source syntax for a voltage source with DC offset 2.5V, amplitude 1V, frequency 10000Hz connected from node 'in' to ground. | Phase 1 -- Element Identification
A sinusoidal voltage source uses the V element with SIN waveform. General syntax:
V<name> <n+> <n-> SIN(<offset> <amplitude> <frequency> [<delay> <damping>])
Amplitude is peak value, not RMS.
Phase 2 -- Parameter Mapping
-> substituting: name=Vin, n+=in, n-=0, offset=2.5, amplitude=... |
Write an ngspice-compatible netlist for a first-order RL high-pass filter with fc=200Hz, R=4.7k, L=82mH. | Phase 1 - Circuit Identification
An RL high-pass filter places the resistor in series and the inductor to ground. At high frequencies the inductor is high impedance, blocking the shunt path and passing the signal. At low frequencies the inductor shorts the output. fc = R/(2piL).
Phase 2 - Design Equations
fc = R/(2pi*... |
Write the ngspice SIN source syntax for a voltage source with DC offset 5V, amplitude 0.5V, frequency 60Hz connected from node 'in' to ground. | Phase 1 -- Element Identification
A sinusoidal voltage source uses the V element with SIN waveform. General syntax:
V<name> <n+> <n-> SIN(<offset> <amplitude> <frequency> [<delay> <damping>])
Amplitude is peak value, not RMS.
Phase 2 -- Parameter Mapping
-> substituting: name=Vin, n+=in, n-=0, offset=5, amplitude=0.... |
Provide a complete SPICE netlist for a peak detector with hold capacitor C=120nF, discharge resistor R=1Meg. | Phase 1 - Circuit Identification
A peak detector captures and holds the maximum amplitude of the input. The diode charges the capacitor to Vpeak. Between peaks, the capacitor discharges slowly through R (tau = RC >> 1/f), maintaining the peak voltage at the output.
Phase 2 - Design Equations
-> substituting: C = 120... |
Write an ngspice-compatible netlist for a RC phase-shift oscillator with f0=2kHz, R=39k, C=820pF. | Phase 1 - Circuit Identification
An RC phase-shift oscillator uses a BJT common-emitter amplifier with three cascaded RC sections each contributing 60deg phase shift (180deg total). Combined with the amplifier's 180deg inversion, the loop phase is 360deg. Barkhausen criterion met when |Av| >= 29.
Phase 2 - Design Equa... |
Perform an AC frequency sweep on a RC Low-Pass filter with fc=1kHz, R=1k, C=4.7nF. Use 20 points per decade. | Phase 1 -- Circuit Identification
A first-order RC Low-Pass filter (R in series, C to ground) has a -3dB point at fc = 1/(2*pi*R*C). AC analysis sweeps the input frequency to reveal gain and phase vs. frequency.
Phase 2 -- Design Equations
fc = 1/(2*pi*R*C) = 1kHz
-> substituting: R=1k, C=4.7nF, fc_actual=33.86kHz
S... |
Produce a SPICE netlist for a BJT emitter follower (common-collector) achieving Ic=15.0mA, Vcc=18V, Re=560. | Phase 1 -- Circuit Identification
A BJT emitter follower (common-collector) provides unity voltage gain with high input impedance and low output impedance. Vout tracks Vin minus Vbe (~0.7V). Useful as a buffer stage.
Phase 2 -- Design Equations
Ic = Ve/Re = 15.0mA
-> substituting: Re=560 Ohm, Ve=8.400V, Vb=9.100V
Ve... |
Write an ngspice-compatible netlist for a bridge rectifier with Vp=30V AC, Rl=5.1k. | Phase 1 - Circuit Identification
A bridge rectifier uses four diodes arranged in a bridge. Both half-cycles are rectified, routing current through the load in the same direction. No centre-tap transformer needed. PIV per diode = Vp.
Phase 2 - Design Equations
-> substituting: Rl = 5.1 k
Vdc = 2Vp/pi ~= 19.1 V
PIV pe... |
Produce a SPICE netlist for a BJT emitter follower (common-collector) achieving Ic=8.0mA, Vcc=12V, Re=470. | Phase 1 -- Circuit Identification
A BJT emitter follower (common-collector) provides unity voltage gain with high input impedance and low output impedance. Vout tracks Vin minus Vbe (~0.7V). Useful as a buffer stage.
Phase 2 -- Design Equations
Ic = Ve/Re = 8.0mA
-> substituting: Re=470 Ohm, Ve=3.760V, Vb=4.460V
Ve ... |
Design a BJT transistor switch with Vcc=5V, Rl=330, Rb=2.2k. | Phase 1 - Circuit Identification
A BJT switch drives the transistor between cutoff (OFF) and saturation (ON). In saturation Vce ~= 0.2 V. The base resistor limits base current to ensure hard saturation with 10* overdrive.
Phase 2 - Design Equations
Ic = Vcc/Rl = 15.2 mA
Ib_min = Ic/beta = Ic/200
Rb = (Vin - Vbe)/(10*I... |
Write the ngspice SIN source syntax for a voltage source with DC offset 5V, amplitude 1V, frequency 50Hz connected from node 'in' to ground. | Phase 1 -- Element Identification
A sinusoidal voltage source uses the V element with SIN waveform. General syntax:
V<name> <n+> <n-> SIN(<offset> <amplitude> <frequency> [<delay> <damping>])
Amplitude is peak value, not RMS.
Phase 2 -- Parameter Mapping
-> substituting: name=Vin, n+=in, n-=0, offset=5, amplitude=1,... |
The following SPICE netlist contains a bug. Identify the fault and provide the corrected netlist.
* Inverting Op-Amp Amplifier — Av=-100, R1=4.7k, Rf=470k
.subckt OPAMP inp inn vcc vee out
EAMP out 0 inp inn 100k
.ends OPAMP
Vin in 0 AC 1 DC 0
R1 in inv_node 4.7k
Rf inv_node out_node 470k
X1 0 inv_node vcc vee out_nod... | Phase 1 - Fault Localization
Examining the netlist line by line reveals: The netlist is missing the mandatory .end statement; ngspice cannot parse an incomplete file.
Phase 2 - Root Cause Analysis
This fault prevents correct operation because it violates a fundamental SPICE or circuit rule. Without correction the simu... |
Construct an ngspice netlist for a negative diode clipper with clip level -3.3V, Rs=5.1k. | Phase 1 - Circuit Identification
A negative clipper limits Vout to -3.3 V. When Vin < -3.3 V, the diode conducts and clamps. Above this level the diode is reverse biased and signal passes.
Phase 2 - Design Equations
Output: Vout = max(Vin, -3.3)
Rs limits current during clamping.
Phase 3 - Component Selection
Rs -> sn... |
Construct an ngspice netlist for a NMOS enhancement-mode switch with Vdd=5V, Rl=390, Rg=120. | Phase 1 - Circuit Identification
An NMOS switch turns ON when Vgs > Vth (~= 2 V). No DC gate current, so no base resistor current drain. Gate resistor prevents oscillation and limits dv/dt on the gate.
Phase 2 - Design Equations
-> substituting: Vdd = 5, Rg = 120 Ohm, Rl = 390 Ohm
ON condition: Vgs = 3.3 V or 5 V > ... |
Write a minimal ngspice .subckt definition for 'OPAMP' with ports 'in', 'inn', 'q'. Use a VCVS with gain=100k. | Phase 1 -- Element Identification
A subcircuit block in SPICE uses .subckt/.ends. General syntax:
.subckt <name> <port1> [<port2> ...]
<internal elements>
.ends <name>
Port names are local. Instantiate with X<instance>.
Phase 2 -- Parameter Mapping
-> substituting: name=OPAMP, ports=in inn q
Phase 3 -- Usage Notes
... |
Build a Wien-bridge oscillator circuit that provides f0=50kHz, R=1k, C=3.3nF. | Phase 1 - Circuit Identification
A Wien-bridge oscillator uses a non-inverting op-amp with a Wien-bridge frequency-selective network. At f0, the bridge gives +1/3 gain and 0deg phase shift. With Av = 3 (Rf = 2Rg), the Barkhausen criterion is met.
Phase 2 - Design Equations
f0 = 1/(2piRC) = 50kHz
-> substituting: R=1... |
Help me design a AC circuit in SPICE. | Phase 1 -- Clarification Needed
The request is underspecified. To generate the correct SPICE netlist, the following information is required:
1. Circuit type and topology (e.g. low-pass RC filter, BJT common-emitter amplifier)?
2. Target specifications: frequency, gain, voltage, or current values?
3. Component values (... |
Construct an ngspice netlist for a peak detector with hold capacitor C=27nF, discharge resistor R=160k. | Phase 1 - Circuit Identification
A peak detector captures and holds the maximum amplitude of the input. The diode charges the capacitor to Vpeak. Between peaks, the capacitor discharges slowly through R (tau = RC >> 1/f), maintaining the peak voltage at the output.
Phase 2 - Design Equations
-> substituting: R = 160... |
Generate a SPICE netlist for a BJT transistor switch achieving Vcc=9V, Rl=160, Rb=560. | Phase 1 - Circuit Identification
A BJT switch drives the transistor between cutoff (OFF) and saturation (ON). In saturation Vce ~= 0.2 V. The base resistor limits base current to ensure hard saturation with 10* overdrive.
Phase 2 - Design Equations
-> substituting: Vcc = 9, Rb = 560 Ohm, Rl = 160 Ohm
Ic = Vcc/Rl = 5... |
Design a non-inverting op-amp amplifier with a voltage gain of +20 V/V. Use R1=22kOhm. Model the op-amp as an ideal VCVS. Provide topology selection reasoning, derive Rf from the gain equation, and write the complete ngspice netlist. | Phase 1 -- Circuit Identification
Specification: non-inverting amplifier, Gain = +20 V/V, R1 = 22kOhm.
Topology selection: non-inverting op-amp configuration.
- Signal applied directly to the non-inverting (+) input.
- Output in phase with input (no inversion).
- Input impedance is essentially infinite (op-amp in... |
Implement a NMOS enhancement-mode switch in SPICE achieving Vdd=24V, Rl=360, Rg=3.6k. | Phase 1 - Circuit Identification
An NMOS switch turns ON when Vgs > Vth (~= 2 V). No DC gate current, so no base resistor current drain. Gate resistor prevents oscillation and limits dv/dt on the gate.
Phase 2 - Design Equations
-> substituting: Vdd = 24, Rg = 3.6 k, Rl = 360 Ohm
ON condition: Vgs = 3.3 V or 5 V > V... |
Create a op-amp differentiator netlist with f0=2kHz, Cin=2.7nF, Rf=30k, τ=81.0μs. | Phase 1 - Circuit Identification
An op-amp differentiator swaps R and C of the integrator: input capacitor and feedback resistor give Vout = -RC*dVin/dt. Gain increases at +20 dB/decade with frequency.
Phase 2 - Design Equations
-> substituting: f0 = 2 kHz, Rf = 30 k
Transfer function: H(s) = -sRC
Time constant: tau... |
Implement a RLC series resonant circuit in SPICE achieving f0=20kHz, R=100, L=12mH, C=5.6nF. | Phase 1 - Circuit Identification
A series RLC circuit exhibits resonance when XL = XC. At resonance f0, impedance is minimum (= R) and current is maximum. Q factor determines bandwidth: BW = f0/Q.
Phase 2 - Design Equations
f0 = 1/(2pisqrt(LC)) = 20kHz
-> substituting: L=12mH, C=5.6nF
Choose L, then C = 1/(2pi*f0)_/... |
Design a non-inverting op-amp amplifier with gain of +51 V/V, Rg=1.6k, Rf=82k. | Phase 1 - Circuit Identification
A non-inverting amplifier applies input directly to the op-amp positive (+) terminal. Negative feedback through Rf and Rg (to ground) sets gain. Output is in phase with input. Gain = 1 + Rf/Rg.
Phase 2 - Design Equations
-> substituting: Rf = 82 k, Rg = 1.6 k
Closed-loop gain: Av = 1... |
The following SPICE netlist contains a bug. Identify the fault and provide the corrected netlist.
Vin in 0 AC 2 DC 0
R1 in out 10k
C1 out 0 10nF
.ac dec 20 10 10Meg
.end | Phase 1 -- Fault Localization
Examining the netlist line by line reveals: The first line of the netlist is not a title comment. In ngspice the first line is ALWAYS treated as the title and is ignored as a comment. Here 'Vin in 0 AC ...' is being consumed as the title, so the voltage source is silently discarded and the... |
Implement a RC phase-shift oscillator in SPICE achieving f0=10kHz, R=8.2k, C=820pF. | Phase 1 - Circuit Identification
An RC phase-shift oscillator uses a BJT common-emitter amplifier with three cascaded RC sections each contributing 60deg phase shift (180deg total). Combined with the amplifier's 180deg inversion, the loop phase is 360deg. Barkhausen criterion met when |Av| >= 29.
Phase 2 - Design Equa... |
Create a Colpitts LC oscillator netlist with f0≈50kHz, L=12uH, C1=1.8uF, C2=1.8uF. | Phase 1 - Circuit Identification
A Colpitts oscillator uses an LC tank for resonance with capacitive voltage division for feedback. The tank has inductor L in parallel with series C1-C2. Feedback to the base is taken from the C1-C2 junction. Oscillation condition: gm >= C1/C2 * 1/Rp.
Phase 2 - Design Equations
f0 = 1/... |
Create a NMOS common-gate amplifier netlist with Id=10.0mA, Vdd=6V, Vg=4V, Rd=300. | Phase 1 - Circuit Identification
In a common-gate configuration the gate is tied to fixed DC bias (AC bypassed). Input enters the source; output is at the drain. Low Zin (~=1/gm) and high Zout. Current gain ~= 1; high voltage gain. Used in RF circuits.
Phase 2 - Design Equations
-> substituting: Vdd = 6
Id = 10.0 mA... |
Write an ngspice-compatible netlist for a positive diode clipper with clip level +7.5V, Rs=4.7k. | Phase 1 - Circuit Identification
A positive clipper limits Vout to +7.5 V. When Vin > 7.5 V, the diode conducts and clamps the output. Rs limits diode current and allows the clipper to work with varying input levels.
Phase 2 - Design Equations
Output: Vout = min(Vin, 7.5)
Rs limits peak diode current and provides inpu... |
Produce a SPICE netlist for a NMOS enhancement-mode switch achieving Vdd=3.3V, Rl=680, Rg=1.8k. | Phase 1 - Circuit Identification
An NMOS switch turns ON when Vgs > Vth (~= 2 V). No DC gate current, so no base resistor current drain. Gate resistor prevents oscillation and limits dv/dt on the gate.
Phase 2 - Design Equations
-> substituting: Vdd = 3.3, Rg = 1.8 k, Rl = 680 Ohm
ON condition: Vgs = 3.3 V or 5 V > ... |
Construct an ngspice netlist for a op-amp differentiator with f0=10kHz, Cin=150nF, Rf=110, τ=16.5μs. | Phase 1 - Circuit Identification
An op-amp differentiator swaps R and C of the integrator: input capacitor and feedback resistor give Vout = -RC*dVin/dt. Gain increases at +20 dB/decade with frequency.
Phase 2 - Design Equations
-> substituting: f0 = 10 kHz, Rf = 110 Ohm
Transfer function: H(s) = -sRC
Time constant:... |
Construct an ngspice netlist for a BJT transistor switch with Vcc=3.3V, Rl=390, Rb=3.9k. | Phase 1 - Circuit Identification
A BJT switch drives the transistor between cutoff (OFF) and saturation (ON). In saturation Vce ~= 0.2 V. The base resistor limits base current to ensure hard saturation with 10* overdrive.
Phase 2 - Design Equations
Ic = Vcc/Rl = 8.5 mA
Ib_min = Ic/beta = Ic/200
Rb = (Vin - Vbe)/(10*Ib... |
Design a RLC series resonant circuit with f0=20kHz, R=43, L=180uH, C=330nF. | Phase 1 - Circuit Identification
A series RLC circuit exhibits resonance when XL = XC. At resonance f0, impedance is minimum (= R) and current is maximum. Q factor determines bandwidth: BW = f0/Q.
Phase 2 - Design Equations
f0 = 1/(2pisqrt(LC)) = 20kHz
-> substituting: L=180uH, C=330nF
Choose L, then C = 1/(2pi*f0)_... |
Produce a SPICE netlist for a op-amp integrator achieving f0=2kHz, R=2k, C=39nF, τ=0.078ms. | Phase 1 - Circuit Identification
An op-amp integrator replaces the feedback resistor with a capacitor. Output: Vout = -(1/RC)_Vin dt. Gain rolls off at -20 dB/decade below the corner frequency.
Phase 2 - Design Equations
-> substituting: f0 = 2 kHz, R = 2 k, C = 39 nF
Transfer function: H(s) = -1/(sRC)
Corner: f0 = ... |
Create a BJT transistor switch netlist with Vcc=9V, Rl=160, Rb=560. | Phase 1 - Circuit Identification
A BJT switch drives the transistor between cutoff (OFF) and saturation (ON). In saturation Vce ~= 0.2 V. The base resistor limits base current to ensure hard saturation with 10* overdrive.
Phase 2 - Design Equations
-> substituting: Vcc = 9, Rb = 560 Ohm, Rl = 160 Ohm
Ic = Vcc/Rl = 5... |
Build a resistive voltage divider circuit that provides Vin=9V, Vout=4.5V, R1=39k, R2=39k. | Phase 1 - Circuit Identification
A resistive voltage divider uses two series resistors to produce a fraction of the input. Vout = Vin * R2/(R1+R2). Output impedance = R1_R2 (must be << load impedance).
Phase 2 - Design Equations
-> substituting: Vin = 9
Ratio: Vout/Vin = R2/(R1+R2) = 4.5/9 = 0.5
Choose R2, then R1 =... |
Build a first-order RC low-pass filter circuit that provides fc=5kHz, R=1.8k, C=18nF. | Phase 1 - Circuit Identification
A first-order RC low-pass filter passes low frequencies and attenuates high frequencies at -20 dB/decade above fc = 1/(2piRC). R is in series; C shunts to ground.
Phase 2 - Design Equations
-> substituting: fc = 5 kHz, R = 1.8 k, C = 18 nF
fc = 1/(2pi*R*C) = 5kHz
RC = 1/(2pi*fc) = 0.... |
Provide a complete SPICE netlist for a RLC series resonant circuit with f0=5kHz, R=39, L=82mH, C=12nF. | Phase 1 - Circuit Identification
A series RLC circuit exhibits resonance when XL = XC. At resonance f0, impedance is minimum (= R) and current is maximum. Q factor determines bandwidth: BW = f0/Q.
Phase 2 - Design Equations
f0 = 1/(2pisqrt(LC)) = 5kHz
-> substituting: L=82mH, C=12nF
Choose L, then C = 1/(2pi*f0)_/L.... |
Design a peak detector with hold capacitor C=180nF, discharge resistor R=10k. | Phase 1 - Circuit Identification
A peak detector captures and holds the maximum amplitude of the input. The diode charges the capacitor to Vpeak. Between peaks, the capacitor discharges slowly through R (tau = RC >> 1/f), maintaining the peak voltage at the output.
Phase 2 - Design Equations
-> substituting: R = 10 ... |
Produce a SPICE netlist for a NMOS common-source amplifier achieving Id=10.0mA, Vdd=18V, Rd=910, Rs=180. | Phase 1 - Circuit Identification
A common-source MOSFET amplifier applies input to the gate and takes output at the drain. The source is AC-bypassed. Rd sets voltage gain (Av = -gm*Rd). Gate draws no DC current, simplifying bias.
Phase 2 - Design Equations
-> substituting: Vdd = 18
Drain current: Id = 10.0 mA
Rd = V... |
Produce a SPICE netlist for a inverting Schmitt trigger achieving Vhys=1.0V, ±18V, R1=1.3k, Rf=24k. | Phase 1 - Circuit Identification
An inverting Schmitt trigger uses positive feedback to the non-inverting (+) terminal to create hysteresis. Upper threshold VUT and lower threshold VLT differ by Vhys, preventing false triggering on noisy signals.
Phase 2 - Design Equations
-> substituting: Rf = 24 k
Vhys = 2*Vsat*R1... |
Perform an AC frequency sweep on a RC High-Pass filter with fc=50kHz, R=22k, C=470nF. Use 20 points per decade. | Phase 1 -- Circuit Identification
A first-order RC High-Pass filter (C in series, R to ground) has a -3dB point at fc = 1/(2*pi*R*C). AC analysis sweeps the input frequency to reveal gain and phase vs. frequency.
Phase 2 -- Design Equations
fc = 1/(2*pi*R*C) = 50kHz
-> substituting: R=22k, C=470nF, fc_actual=0.02kHz... |
Construct an ngspice netlist for a RC phase-shift oscillator with f0=10kHz, R=3.9k, C=1.8nF. | Phase 1 - Circuit Identification
An RC phase-shift oscillator uses a BJT common-emitter amplifier with three cascaded RC sections each contributing 60deg phase shift (180deg total). Combined with the amplifier's 180deg inversion, the loop phase is 360deg. Barkhausen criterion met when |Av| >= 29.
Phase 2 - Design Equa... |
Build a first-order RC high-pass filter circuit that provides fc=2kHz, R=100k, C=820pF. | Phase 1 - Circuit Identification
A first-order RC high-pass filter passes high frequencies and blocks DC. C is in series; R shunts to ground. Attenuation rises at +20 dB/decade below fc.
Phase 2 - Design Equations
fc = 1/(2pi*R*C) = 2kHz
-> substituting: R=100k, C=820pF
Phase 3 - Component Selection
R -> snapped to ... |
Give me a SPICE netlist for a signal processor. | Phase 1 -- Clarification Needed
The request is underspecified. To generate the correct SPICE netlist, the following information is required:
1. Circuit type and topology (e.g. low-pass RC filter, BJT common-emitter amplifier)?
2. Target specifications: frequency, gain, voltage, or current values?
3. Component values (... |
Write an ngspice-compatible netlist for a first-order RC high-pass filter with fc=100kHz, R=2.7k, C=560pF. | Phase 1 - Circuit Identification
A first-order RC high-pass filter passes high frequencies and blocks DC. C is in series; R shunts to ground. Attenuation rises at +20 dB/decade below fc.
Phase 2 - Design Equations
fc = 1/(2pi*R*C) = 100kHz
-> substituting: R=2.7k, C=560pF
Phase 3 - Component Selection
R -> snapped t... |
Provide a complete SPICE netlist for a RC phase-shift oscillator with f0=2kHz, R=24k, C=1.5nF. | Phase 1 - Circuit Identification
An RC phase-shift oscillator uses a BJT common-emitter amplifier with three cascaded RC sections each contributing 60deg phase shift (180deg total). Combined with the amplifier's 180deg inversion, the loop phase is 360deg. Barkhausen criterion met when |Av| >= 29.
Phase 2 - Design Equa... |
Create a BJT current mirror netlist with Iref=0.5mA, Vcc=6V, Rref=11k. | Phase 1 - Circuit Identification
A BJT current mirror uses two matched transistors sharing the same Vbe. Q1 is diode-connected, setting Vbe. Q2 copies the same Vbe, mirroring the reference current. Output tracks Iref independent of load voltage (matched devices assumed).
Phase 2 - Design Equations
-> substituting: V... |
Provide a complete SPICE netlist for a negative diode clipper with clip level -2.0V, Rs=22k. | Phase 1 - Circuit Identification
A negative clipper limits Vout to -2.0 V. When Vin < -2.0 V, the diode conducts and clamps. Above this level the diode is reverse biased and signal passes.
Phase 2 - Design Equations
Output: Vout = max(Vin, -2.0)
Rs limits current during clamping.
Phase 3 - Component Selection
Rs -> sn... |
Implement a NMOS common-source amplifier in SPICE achieving Id=15.0mA, Vdd=3.3V, Rd=110, Rs=22. | Phase 1 - Circuit Identification
A common-source MOSFET amplifier applies input to the gate and takes output at the drain. The source is AC-bypassed. Rd sets voltage gain (Av = -gm*Rd). Gate draws no DC current, simplifying bias.
Phase 2 - Design Equations
-> substituting: Vdd = 3.3
Drain current: Id = 15.0 mA
Rd = ... |
Implement a NMOS source follower (common-drain) in SPICE achieving Id=8.0mA, Vdd=9V, Rs=560. | Phase 1 - Circuit Identification
A source follower applies signal to the gate and takes output at the source. Av ~= 1, no phase inversion. Very high Zin (gate); low Zout (~=1/gm). Used as buffer between high-Z source and low-Z load.
Phase 2 - Design Equations
-> substituting: Vdd = 9
Av ~= gm*Rs/(1+gm*Rs) ~= 1
Rs = ... |
Build a RC phase-shift oscillator circuit that provides f0=10kHz, R=2.4k, C=2.7nF. | Phase 1 - Circuit Identification
An RC phase-shift oscillator uses a BJT common-emitter amplifier with three cascaded RC sections each contributing 60deg phase shift (180deg total). Combined with the amplifier's 180deg inversion, the loop phase is 360deg. Barkhausen criterion met when |Av| >= 29.
Phase 2 - Design Equa... |
Give me an ngspice netlist for a RLC series resonant circuit with f0=50kHz, R=43, L=39mH, C=270pF. | Phase 1 - Circuit Identification
A series RLC circuit exhibits resonance when XL = XC. At resonance f0, impedance is minimum (= R) and current is maximum. Q factor determines bandwidth: BW = f0/Q.
Phase 2 - Design Equations
f0 = 1/(2pisqrt(LC)) = 50kHz
-> substituting: L=39mH, C=270pF
Choose L, then C = 1/(2pi*f0)_/... |
Design a inverting Schmitt trigger with Vhys=1.0V, ±18V, R1=4.3k, Rf=75k. | Phase 1 - Circuit Identification
An inverting Schmitt trigger uses positive feedback to the non-inverting (+) terminal to create hysteresis. Upper threshold VUT and lower threshold VLT differ by Vhys, preventing false triggering on noisy signals.
Phase 2 - Design Equations
-> substituting: Rf = 75 k
Vhys = 2*Vsat*R1... |
Build a full-wave centre-tap rectifier circuit that provides Vp=15V per half, Rl=910. | Phase 1 - Circuit Identification
A full-wave centre-tap rectifier uses two diodes with a centre-tapped transformer. Each diode conducts on alternate half-cycles, both producing the same polarity output. Vdc = 2Vp/pi ~= 9.55 V. Ripple frequency = 2* input.
Phase 2 - Design Equations
-> substituting: Rl = 910 Ohm
Vdc ... |
The following SPICE netlist contains a bug. Identify the fault and provide the corrected netlist.
* NMOS Current Mirror
.model NMOS1 NMOS(VTO=1 KP=2m W=100u L=1u)
Vdd vdd 0 DC 3.3
Rref vdd ref 4.7k
M1 ref ref 0 0 NMOS1
M2 out ref 0 0 NMOS1
Rl out 0 2.2k
.ac dec 10 1 1Meg
.end | Phase 1 -- Fault Localization
Examining the netlist line by line reveals: The analysis command is '.ac' but this is a DC current mirror. There is no AC source in the netlist, so '.ac' will return zero response everywhere. The correct analysis is '.op' to verify the mirror's DC operating point and confirm Iout = Iref.
... |
Produce a SPICE netlist for a zener voltage reference achieving Vz=5.6V, Vin=15.6V, Iz=8.0mA, Rs=1.2k. | Phase 1 - Circuit Identification
A zener diode reference operates the zener in reverse breakdown to produce stable output Vz. Series resistor Rs limits current. Zener voltage is largely independent of Iz over its operating range, giving good line regulation.
Phase 2 - Design Equations
Rs = (Vin - Vz)/Iz = (15.6 - 5.6)... |
Design a non-inverting op-amp amplifier with a voltage gain of +47 V/V. Use R1=10kOhm. Model the op-amp as an ideal VCVS. Provide topology selection reasoning, derive Rf from the gain equation, and write the complete ngspice netlist. | Phase 1 -- Circuit Identification
Specification: non-inverting amplifier, Gain = +47 V/V, R1 = 10kOhm.
Topology selection: non-inverting op-amp configuration.
- Signal applied directly to the non-inverting (+) input.
- Output in phase with input (no inversion).
- Input impedance is essentially infinite (op-amp in... |
Provide a complete SPICE netlist for a NMOS source follower (common-drain) with Id=20.0mA, Vdd=5V, Rs=120. | Phase 1 - Circuit Identification
A source follower applies signal to the gate and takes output at the source. Av ~= 1, no phase inversion. Very high Zin (gate); low Zout (~=1/gm). Used as buffer between high-Z source and low-Z load.
Phase 2 - Design Equations
-> substituting: Vdd = 5
Av ~= gm*Rs/(1+gm*Rs) ~= 1
Rs = ... |
Create a BJT common-emitter amplifier netlist with Ic=20.0mA, Vcc=18V, Rc=430, Re=43. | Phase 1 - Circuit Identification
A common-emitter amplifier uses a BJT with input at the base and output at the collector. Voltage divider bias (R1, R2) sets the DC Q-point. Rc sets voltage gain; Re stabilises operating point thermally.
Phase 2 - Design Equations
-> substituting: Vcc = 18, Rc = 430 Ohm, Re = 43 Ohm
... |
Create a NMOS source follower (common-drain) netlist with Id=3.0mA, Vdd=12V, Rs=2k. | Phase 1 - Circuit Identification
A source follower applies signal to the gate and takes output at the source. Av ~= 1, no phase inversion. Very high Zin (gate); low Zout (~=1/gm). Used as buffer between high-Z source and low-Z load.
Phase 2 - Design Equations
Av ~= gm*Rs/(1+gm*Rs) ~= 1
Rs = (Vdd/2)/Id ~= 2.0 kOhm
->... |
Construct an ngspice netlist for a RLC series bandpass filter with f0=100kHz, BW=500Hz, Q=200.0, R=390. | Phase 1 - Circuit Identification
A series RLC bandpass filter passes frequencies near resonance and attenuates both lower and higher frequencies. BW = R/(2piL). Q = f0/BW indicates selectivity.
Phase 2 - Design Equations
-> substituting: f0 = 100 kHz, R = 390 Ohm, Q = 200, BW = 500 Hz
f0 = 1/(2pisqrtLC) = 100kHz
BW ... |
Produce a SPICE netlist for a bridge rectifier with capacitor filter achieving Vp=6V, Iload=200.0mA, ripple<0.5V, C=8.2mF. | Phase 1 - Circuit Identification
A capacitor-filter DC supply follows a bridge rectifier with a large electrolytic capacitor. The capacitor charges to near Vp and discharges through the load between peaks, reducing ripple. Larger C or higher frequency yields less ripple.
Phase 2 - Design Equations
Ripple: Vr = Il/(f*C... |
Give me an ngspice netlist for a NMOS common-source amplifier with Id=10.0mA, Vdd=12V, Rd=620, Rs=120. | Phase 1 - Circuit Identification
A common-source MOSFET amplifier applies input to the gate and takes output at the drain. The source is AC-bypassed. Rd sets voltage gain (Av = -gm*Rd). Gate draws no DC current, simplifying bias.
Phase 2 - Design Equations
-> substituting: Vdd = 12
Drain current: Id = 10.0 mA
Rd = V... |
Perform an AC frequency sweep on a RC Low-Pass filter with fc=10kHz, R=1k, C=22nF. Use 20 points per decade. | Phase 1 -- Circuit Identification
A first-order RC Low-Pass filter (R in series, C to ground) has a -3dB point at fc = 1/(2*pi*R*C). AC analysis sweeps the input frequency to reveal gain and phase vs. frequency.
Phase 2 -- Design Equations
fc = 1/(2*pi*R*C) = 10kHz
-> substituting: R=1k, C=22nF, fc_actual=7.23kHz
Sw... |
Write the ngspice .ac command for a frequency sweep: type='dec', 50 points per interval, from 1Hz to 10000000Hz. | Phase 1 -- Element Identification
The .ac command performs AC small-signal analysis. General syntax:
.ac <type> <points> <fstart> <fstop>
Types: dec (pts per decade), oct (per octave), lin (total linear pts).
Phase 2 -- Parameter Mapping
-> substituting: type=dec, points=50, fstart=1, fstop=10000000
Phase 3 -- Usag... |
Generate a SPICE netlist for a two-input inverting summing amplifier achieving gains −10.0/−10.0, Rf=43k, R1=4.3k, R2=4.3k. | Phase 1 - Circuit Identification
A summing amplifier uses the virtual-ground property of the inverting terminal to sum multiple input currents. Each input is scaled by its own resistor, then summed into Rf. Output: Vout = -(Rf/R1*V1 + Rf/R2*V2).
Phase 2 - Design Equations
Vout = -(Rf/R1 * V1 + Rf/R2 * V2)
-> substit... |
Design a first-order RL low-pass filter with fc=500Hz, R=200, L=68mH. | Phase 1 - Circuit Identification
An RL low-pass filter places an inductor in series and resistor to ground. Low inductive reactance at low frequencies passes the signal; increasing XL above fc attenuates at -20 dB/decade. fc = R/(2piL).
Phase 2 - Design Equations
fc = R/(2pi*L) = 500Hz
-> substituting: L=68mH
L = R/... |
Implement a RLC series bandpass filter in SPICE achieving f0=2kHz, BW=400Hz, Q=5.0, R=1.2k. | Phase 1 - Circuit Identification
A series RLC bandpass filter passes frequencies near resonance and attenuates both lower and higher frequencies. BW = R/(2piL). Q = f0/BW indicates selectivity.
Phase 2 - Design Equations
f0 = 1/(2pisqrtLC) = 2kHz
BW = R/(2piL) = 400Hz
-> substituting: R=1.2k
Q = f0/BW = 5.0
Design: ... |
Provide a complete SPICE netlist for a NMOS enhancement-mode switch with Vdd=12V, Rl=1.5k, Rg=1.5k. | Phase 1 - Circuit Identification
An NMOS switch turns ON when Vgs > Vth (~= 2 V). No DC gate current, so no base resistor current drain. Gate resistor prevents oscillation and limits dv/dt on the gate.
Phase 2 - Design Equations
-> substituting: Vdd = 12, Rg = 1.5 k, Rl = 1.5 k
ON condition: Vgs = 3.3 V or 5 V > Vth... |
Design a first-order RC high-pass filter with fc=1kHz, R=47k, C=100nF. | Phase 1 -- Circuit Identification
A first-order RC high-pass filter passes high frequencies and attenuates low frequencies at +20 dB/decade below fc = 1/(2*pi*R*C). C is in series; R shunts to ground.
Phase 2 -- Design Equations
fc = 1/(2*pi*R*C) = 1kHz
-> substituting: R=47k, C=100nF, fc_actual=0.03kHz
RC = 1/(2*pi... |
Give me an ngspice netlist for a Colpitts LC oscillator with f0≈200kHz, L=56uH, C1=22nF, C2=22nF. | Phase 1 - Circuit Identification
A Colpitts oscillator uses an LC tank for resonance with capacitive voltage division for feedback. The tank has inductor L in parallel with series C1-C2. Feedback to the base is taken from the C1-C2 junction. Oscillation condition: gm >= C1/C2 * 1/Rp.
Phase 2 - Design Equations
f0 = 1/... |
Write an ngspice-compatible netlist for a non-inverting op-amp amplifier with gain of +68 V/V, Rg=16k, Rf=1.1Meg. | Phase 1 - Circuit Identification
A non-inverting amplifier applies input directly to the op-amp positive (+) terminal. Negative feedback through Rf and Rg (to ground) sets gain. Output is in phase with input. Gain = 1 + Rf/Rg.
Phase 2 - Design Equations
-> substituting: Rf = 1.1 Ohm, Rg = 16 k
Closed-loop gain: Av =... |
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